Ip - Esc ’ 11 Co - Designed Cache Coherency Architecture for Embedded Multicore Systems

نویسنده

  • Jussara Marandola
چکیده

One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for embedded systems are known to read and write data following memory access patterns. Memory access patterns can be used to optimize cache consistency by prefetching data and reducing the number of memory transactions. In this paper, we present the round-robin method applied to baseline coherency protocol and initial analysis of one hybrid protocol that performs speculative requests when access patterns are detected. We also propose to manage patterns through a dedicated hardware component attached to each core of the processor.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Level-2 Shared Cache versus Level-2 Dedicated Cache for Homogeneous Multicore Embedded Systems

Multicore brings tremendous amount of processing speed. On the contrary, it offers challenges for embedded systems as embedded systems suffer from limited resources. Various cache memory hierarchies are proposed to satisfy the requirements of different systems. Traditionally, level-1 cache memory is dedicated to each core. However, level-2 cache can be shared (like Intel Xenon) or dedicated (li...

متن کامل

Cache-aware static scheduling for hard real-time multicore systems based on communication affinities

The growing need for continuous processing capabilities has led to the development of multicore systems with a complex cache hierarchy. Such multicore systems are generally designed for improving the performance in average case, while hard real-time systems must consider worst-case scenarios. An open challenge is therefore to efficiently schedule hard real-time tasks on a multicore architecture...

متن کامل

An Efficient Non-blocking Multithreaded Embedded System

Most embedded systems are designed to perform one or fewer specific functions. It is important that the hardware and the software must closely interact to achieve maximum efficiency in all of these realms and overcome the drawbacks found in each aspect. This research focuses on designing a totally new Instruction Set Architecture (ISA) as well as hardware that can closely tie together with the ...

متن کامل

Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches

For real-time systems it is important to obtain the accurate worst-case execution time (WCET). Furthermore, how to improve the WCET of applications that run on multicore processors is both significant and challenging as the WCET can be largely affected by the possible inter-core interferences in shared resources such as the shared L2 cache. In order to solve this problem, we propose an innovati...

متن کامل

A Note on Software Partitioning for Embedded Homogenous Multicore Systems

The introduction of homogenous multicore systems for embedded devices in the automotive domain has been started recently. Driver information systems like car navigation are the first application. This paper shows how the software architecture should be designed in order to use the multicore technology efficiently. We will focus on two principles as scheduling algorithms and parallel programming...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2012